A novel 32 bit RISC architecture unifying RISC and DSP

A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit xed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed. With the architecture presented it has been proven that a DSP processor can be implemented using strictly the RISC design philosophy. Besides providing basic 16 bit xed point functionality, the architecture implements a set of DSP instructions that support an e cient mapping of common DSP algorithms to the processor.